1. Field-of the invention
The present invention concerns a device for conversion of frame frequency and number of lines for a high-definition television receiver, more particularly a device for conversion of frame frequency and number of lines for a high-definition television receiver able to receive high-definition input signals emanating more particularly from a high-definition 625 lines, interlaced, 50 Hz (625/2:1/50 Hz) source. The device of the present invention also applies to standard-definition signals such as 625/2:1/50 Hz, PAL, SECAM and MAC signals.
2. Description of the prior art
A frame frequency conversion device for high-definition television receivers has already been proposed in the French patent application no. 89 03861, dated 23rd Mar. 1989, in the name of the Applicant. As shown in FIG. 1, this device comprises essentially an analog-digital converter 1 which receives an input of video signals E such as high-definition 1250/2:1/50 Hz signals in the baseband or compressed in accordance with the HD-MAC procedure in the 625/2:1/50 Hz standard, hereinafter called 625/2:1/50 Hz high-definition signals, or PAL, SECAM or MAC 625/2:1/50 Hz standard signals. The 625/2:1/50 Hz standard signals output from the converter 1 are sent directly to a switching device 3 while the high-definition signals are sent to the device 3 via an ordinary pass-band reduction decoder 2. The switching device 3 sends either 1250/2:1/50 Hz signals or 625/2:1/50 Hz signals to a frequency conversion device 4 as represented in FIG. 2 and described in French patent application no. 89 03861 in the name of the Applicant. This frequency conversion device 4 receives DATV (Digital Assisted Television) information. This DATV signal from the decoder 2 includes movement information MI. The frequency conversion device 4 gives an output signal S used for display on the screen. This output signal S is a 1250/2:1/100 Hz or 900/2:1/100 Hz high-definition signal. In the device shown in FIG. 1, the frame frequency conversion is performed in the circuit 4. To do so, and as represented in FIG. 2, the circuit 4 includes in input an image memory to store two frames, i.e. the even and odd frames, in accordance with the input standard, which is a frame frequency of 50 Hz (frame duration 20 ms). This memory enables this duration to be compressed to half its length, to obtain an output frame frequency of 100 Hz, giving a frame duration of 10 ms. In fact, as represented in FIG. 2, this image memory is made up of four memories 10A, 10B, 10C, 10D enabling storage of the even points of the even frames, the odd points of the even frames, the even points of the odd frames and the odd points of the odd frames. Each memory has a capacity of 1250 lines.times.720 points.times.8 bits to be able to store an image of 1250 lines.times.1440 points, corresponding to a decompressed high-definition image. The use of four memories 10A, 10B, 10C, 10D is intended to restrict the read frequency of the memories to 54 MHz. As described in more detail below, multiplexers 11A, 11B or 12 will make it possible to reconstitute the sample stream at 108 MHz.
In addition, as represented in FIG. 2, the circuit 4 includes a part 4B which will be described in more detail later and which enables filtering, decimation and vertical interpolation operations to be performed. These operations are carried out at the frame frequency required, i.e. 100 Hz in the mode of embodiment represented. The circuit 4 is thus constituted of two distinct parts, a memory 4A enabling frame frequency conversion and a part 4B. However, as described above, part 4A requires a large amount of memory space.